Reduced Hardware Lock Elision

Hardware lock elision (HLE) concurrently executes lock critical sections as hardware transactions, but fallbacks to the original sequential lock fallback path when some hardware transaction fails. Recent software-assisted lock-removal based schemes provide a better concurrency by sacrificing safety (opacity). Hardware transactions can execute at the same time with the lock fallback path as long as they do not try to commit. This limited concurrency is beneficial, but enables hardware transactions to see inconsistent memory states, that may lead to illegal instructions, corrupted memory, and other unsafe behaviors. We propose a novel reduced hardware lock elision algorithm (RH-LE). It provides a safe (and opaque) concurrency between hardware transactions and the lock fallback path. The core idea behind the RH-LE approach is to execute the lock fallback path as a rollback-only hardware transaction, that tracks only the memory writes of the transaction. This special hardware transaction is already introduced in the IBM Power8 ISA specification with the intention to be used only for non-shared writes. We propose to use the rollback-only hardware transaction for all of the writes, shared or non-shared, and in this way to hide all of the write modifications of the lock fallback path till its successful commit. The hiding process preserves opacity of concurrent hardware transactions, and allows read-only hardware transactions to commit even when there is a concurrent fallback execution. Currently, IBM Power8 processors are unavailable for public use, and therefore we implement a software-based simulation of the RH-LE algorithm. It shows that the new lock elision scheme has the potential to be almost 2 times faster than other lock elision techniques.